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Flexible static memory controller (FSMC)
Table 107. FSMC_BCRx bit fields
RM0008
Bit No.
31-15
14
13-10
9
8
7
6
5-4
3-2
1
0
Bit name
EXTMOD
WAITPOL
BURSTEN
FACCEN
MWID
MTYP
MUXEN
MBKEN
Value to set
0x0000
0x0
0x0
Meaningful only if bit 15 is 1
0x0
-
0x1
As needed
0x2 (NOR)
0x1
0x1
Table 108. FSMC_TCRx bit fields
Bit No.
31-20
19-16
15-8
7-4
3-0
Bit name
BUSTURN
DATAST
ADDHLD
ADDSET
Value to set
0x0000
Duration of the last phase of the access (BUSTURN+1 HCLK)
Duration of the second access phase (DATAST+3 HCLK cycles for
read accesses and DATAST+1 HCLK cycles for write accesses).
This value cannot be 0 (minimum is 1)
Duration of the middle phase of the access (ADDHLD+1 HCLK
cycles).This value cannot be 0 (minimum is 1).
Duration of the first access phase (ADDSET+1 HCLK cycles).
19.5.5
430/995
Synchronous burst transactions
The memory clock, CLK, is a submultiple of HCLK according to the value of parameter
CLKDIV.
NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet
this constraint, the FSMC does not issue the clock to the memory during the first internal
clock cycle of the synchronous access (before NADV assertion). This guarantees that the
rising edge of the memory clock occurs in the middle of the NADV low pulse.
Doc ID 13902 Rev 9
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